Ninad Jangle

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Electronics Engineering student at V.J.T.I, Silicon enthusiast, Proficient in Circuit Design, RISC-V, Web Development and Automation.
Gsoc 21’ @FOSSi Foundation | 2nd Prize @7th Delta Advanced Automation Cup | Electronics Head @SRA VJTI

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Week 5


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  1. 1/07/2021:
    • Added variableDB_ scrubber in the tl_verilog.js - the logic required by the tlVerilogGenerator to handle variable generation and operations

  1. 2/07/2021:
  2. 3/07/2021:
    • this.getfieldvalue not returning proper values for the variable data. Worked on fixing the variable logic

  1. 4/07/2021:
    • Completed a course on React with coding all examples

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  1. 5/07/2021:
  2. 6/07/2021:
    • Starting to add custom categories. Reference

  3. 7/07/2021: